A Computer System Includes 64KB Main Memory ✓ Solved

A computer system includes 64KB size main memory (main memory)

A computer system includes 64KB size main memory and 1KB size cache. Blocks of 16 * 8 are made. Use the set associative method, which includes 2 blocks per set. The block in cache is for the LRU method in decision making. It uses Simple Reading Back methods for direct reading in reading and caching (Allocate Write) for reading. Under the assumption that initially the cache is empty, at first access, show which blocks will be placed in the front memory (cache). During the running of the program, at what moments, data transfer occurs between the main memory and the cache. Note: There are 2 arrays which has 20 elements (each element 8 bits) in main memory of this system. Start addresses of these arrays: Array1=$0000, Array2=$0200. A MIPS program will read elements of these arrays one by one (in order) and will compare these elements then will start to write the bigger element (as a result of comparing) to another array by this starting address: Array3=$0410. If we assume the cache memory is empty at the beginning; Where will be placed these arrays in cache memory (which sets, which blocks) for first accesses? And which moments has data transferring between main memory and cache memory while program is running, explain and show it.

Paper For Above Instructions

In a typical computer system, memory hierarchies are essential for efficient data access, particularly when dealing with a set associative cache. This paper discusses a specific scenario where a computer system includes a 64KB main memory and a 1KB cache, utilizing a set associative caching technique with 2 blocks per set. Additionally, this analysis will cover the behavior of the cache during the execution of a MIPS program that processes two arrays sequentially.

Main Memory and Cache Overview

The main memory, with a size of 64KB, is divided into blocks of 16 bytes each (meaning that each block contains 16 elements of 8 bits). With 64KB of memory, which is equivalent to 65536 bytes, we can derive the total number of blocks in main memory:

  • Total blocks in main memory = 64KB / 16 bytes = 4096 blocks

The 1KB cache also consists of blocks of the same size (16 bytes). Therefore, the total number of blocks in the cache is:

  • Total blocks in cache = 1KB / 16 bytes = 64 blocks

Cache Organization

In a set associative cache with 2 blocks per set, the total number of sets in the cache is calculated as follows:

  • Total sets = Total blocks in cache / blocks per set = 64 / 2 = 32 sets

Each set can store two blocks from main memory. The cache uses an LRU (Least Recently Used) mechanism to determine which block to evict when a new block needs to be loaded.

Memory Address Mapping

To understand how the cache maps data from the main memory, we will analyze the address decoding:

  • Each memory address is 16 bits (for 64KB), where the lowest 4 bits (2^4 = 16) determine the byte offset within the block, and the next 5 bits (2^5 = 32) are used for the index into the cache sets.

Thus, the address breakdown will look as follows:

  • Bits 0-3: Block offset (4 bits, 16 bytes)
  • Bits 4-8: Set index (5 bits, defining 32 sets)
  • Bits 9-15: Tag bits (remaining bits that help identify the block)

Objects and Their Addresses

We have two arrays existing in memory as follows:

  • Array1 starts at $0000 and Array1 contains 20 elements (totaling 160 bytes or 20 * 8 bytes).
  • Array2 starts at $0200 and also contains 20 elements, totaling another 160 bytes.
  • Array3 starts at $0410 and will hold the results of comparisons from the two arrays.

First Cache Accesses

As we assume the cache is empty at the start:

  • When accessing Array1, it first reads the block containing addresses ranging from $0000 to $000F (Block 0).
  • This block will be loaded into the cache set corresponding to its computed index derived from address calculation.
  • For example, if the index for this block calculates to Set 0, both block 0 from Array1 is stored in Cache Set 0 (with the other block in LRU under position 0 waiting for an incoming second block).

Subsequent Data Transfers

As the program executes, it iterates through both arrays, moving from one element to the next. Each accessed element may cause cache misses, prompting data transfers. The first few accesses are:

  • Access element 0 of Array1 ($0000): Cache misses, loads Block 0 into Cache Set 0.
  • Access element 1 to 15 of Array1 ($0001 to $000F): Cache hits, continue reading from Cache.
  • Access element 16 of Array1 ($00010): Cache misses, loads Block 1 (new block) into Cache Set 0, evicting the LRU if full.
  • Similar process occurs when accessing Array2, starting from address $0200.

Conclusion

The process of caching elements continues as the MIPS program executes, comparing elements, with the larger being written to Array3. Memory transfers will coincide with cache misses whenever the program accesses data not currently loaded in the cache sets, demonstrating the significance of cache organization and the effects of partially filled memory during execution.

References

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