Computer Architecture Course 320241 Jacobs University Bremen

Computer Architecture Course 320241jacobs University Bremen Novembe

Perform the following arithmetic operations with MIPS code, assuming specific registers for variables and not knowing the 'mul' operation for the third problem. Also, provide binary codes for certain instructions, write MIPS assembler code for array manipulations, and analyze instruction format changes for a reduced register set.

Paper For Above instruction

The assignment encompasses a series of exercises focused on MIPS architecture, instruction encoding, memory access, and instruction format modification. These exercises are designed to deepen understanding of fundamental concepts in computer architecture related to instruction set design, data processing, and memory operations.

Arithmetic Operations in MIPS Assembly

The first task requires writing MIPS code to perform basic arithmetic calculations involving addition, subtraction, and multiplication, with considerations for the constraints of the instruction set. Since the 'mul' instruction is not initially available, multiplication must be implemented using shift and addition. Assuming the registers $t0, $s0, $s1, and $s2 hold variables 'a', 'b', 'c', and 'd' respectively, the assembly code for the given operations is as follows:

# 1. a = b + c

add $t0, $s0, $s1    # $t0 = $s0 + $s1


2. a = b - c + d


sub $t0, $s0, $s1    # $t0 = $s0 - $s1


add $t0, $t0, $s2    # $t0 = $t0 + $s2


3. a = 8 * b (using shifts since 'mul' is not available)


sll $t0, $s0, 3     # $t0 = $s0 

4. a = (2 + b) * 4 (calculate (2 + b) and shift)


addi $t1, $s0, 2     # $t1 = b + 2


sll $t0, $t1, 2     # $t0 = $t1

Each code block is annotated with comments explaining the operation performed.

Binary Codes for MIPS Instructions

The second task involves providing binary representations for the first two instructions from above. MIPS instructions follow specific encoding formats. For simplicity, assuming the R-format for add and sub, and I-format for addi. The binary encoding for an 'add' instruction (e.g., add $t0, $s0, $s1) is constructed as follows:

  • Opcode: 6 bits (000000 for R-type)
  • rs: 5 bits (source register 1)
  • rt: 5 bits (source register 2)
  • rd: 5 bits (destination register)
  • shamt: 5 bits (shift amount, zero for add/sub)
  • funct: 6 bits (specific to the operation, e.g., 100000 for add)

Similarly, the binary encoding for 'sub' is also an R-type with funct code 100010. Example binary encoding for 'add $t0, $s0, $s1' (assuming register mapping: $s0=16, $s1=17, $t0=8):

000000 10000 10001 01000 00000 100000

|---|-----|-----|-----|-----|----------|


Opcode rs   rt   rd   shamt funct

Converting these fields into binary yields the full 32-bit instruction code.

MIPS Memory Access for Array Operations

The third exercise requires writing MIPS assembler code for copying the sum of specific elements from array A into array B. Given the base addresses in registers $s0 (A) and $s1 (B), and the specific array indices, the code proceeds as follows:

# Load A[2] and A[3] addresses and values

lw $t0, 8($s0)    # Load A[2] (offset = 2 * 4 bytes)


lw $t1, 12($s0)   # Load A[3]


Compute sum


add $t2, $t0, $t1


Store into B[5]


sw $t2, 20($s1)   # Store to B[5] (offset = 5 * 4 bytes)

Commented code blocks clarify which operations correspond to each instruction, emphasizing addressing computations and memory accesses.

Memory Access with Variable Index

The fourth task involves memory operations where the index is stored in a variable register. For B[x] = A[x + 2] + A[x + 3], with 'x' in $t0, and base addresses in $s0 and $s1, the code is structured as follows:

# Compute address of A[x + 2]

addi $t1, $t0, 2       # $t1 = x + 2


sll $t1, $t1, 2        # offset = ($t1) * 4 (word size)


add $t2, $s0, $t1      # Effective address for A[x+2]


lw $t3, 0($t2)         # Load A[x+2]


Compute address of A[x + 3]


addi $t4, $t0, 3       # $t4 = x + 3


sll $t4, $t4, 2        # offset = ($t4) * 4


add $t5, $s0, $t4      # Address of A[x+3]


lw $t6, 0($t5)         # Load A[x+3]


Sum the values


add $t7, $t3, $t6


Store into B[x]


sll $t0, $t0, 2        # Offset for B[x]


add $t8, $s1, $t0


sw $t7, 0($t8)

This sequence computes array element addresses dynamically based on variable 'x' and performs the addition and storage accordingly. Comments indicate each step’s purpose.

Instruction Format Modification for Reduced Register Set

The fifth exercise considers how to adapt the MIPS 'addi' instruction format to accommodate only 16 registers instead of 32. The current format uses 5 bits for register fields, allowing for 32 registers (2^5). To reduce to 16, the register specifiers can be shortened to 4 bits each (2^4 =16). This change implies:

  • The opcode remains 6 bits.
  • The rs and rt fields are reduced to 4 bits each, representing registers 0-15.
  • The immediate field remains 16 bits, as it is unaffected by register count.

The main reasoning behind this change is to conserve instruction encoding space and simplify hardware while limiting the total addressable registers. This reduction restricts the number of general-purpose registers available but provides sufficient register access for many applications, optimizing silicon area and instruction decoding complexity.

Conclusion

This compilation of MIPS assembly programming exercises illustrates key concepts such as instruction encoding, architecture constraints, and memory addressing strategies. Understanding these fundamentals is critical for designing efficient instruction sets and optimizing low-level code performance. Modifications like switching to a 16-register format demonstrate architectural trade-offs between complexity and capability, which are central to processor design decisions.

References

  • Hennessy, J. L., & Patterson, D. A. (2019). Computer Organization and Design MIPS Edition: The Hardware/Software Interface. Morgan Kaufmann.
  • Stallings, W. (2018). Computer Organization and Architecture (10th ed.). Pearson.
  • Patterson, D. A., & Hennessy, J. L. (2017). Computer Architecture: A Quantitative Approach (6th ed.). Morgan Kaufmann.
  • Mano, M. M., & Ciletti, M. D. (2017). Digital Design (6th ed.). Pearson.
  • David A. Patterson. (2012). Computer Architecture: A Quantitative Approach. Morgan Kaufmann.
  • Hwang, K., & Briggs, F. A. (2012). Computer Architecture and Parallel Processing. McGraw-Hill.
  • Levine, D. P. (2010). Computer organization and architecture: designing for performance. McGraw-Hill Education.
  • Yale N. T. (2000). Introduction to computer architecture. McGraw-Hill.
  • MIPS Technologies. (2000). MIPS Assembly Language Programming. MIPS Technologies Inc.
  • Nangreave, A. (2015). Assembly Language Programming for MIPS CPU. Springer.

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