Loop Unrolling: 40 Marks Consider The Following Loop

Loop Unrolling 40 Marksconsider The Following Looploop Ld F

Consider the following loop: loop: l.d f4,0(r1) l.d f6,0(r2) mul.d f4,f4,f0 add.d f4,f4,f6 s.d f4,0(r1) daddui r1,r1,#-8 daddui r2,r2,#-8 bnez r1,loop

Our default is that FP arithmetics have 4 x-boxes. Your task involves understanding dependency graphs, stalls, loop unrolling, and dynamic instruction scheduling, among other concepts related to processor optimizations and pipeline behavior.

Paper For Above instruction

Part 1 - Dependency Graph and Stall Analysis

a) Dependency Graph Construction

In analyzing the loop, the first step involves constructing the flow-dependence graph for the initial six instructions, namely l1 to s1. The instructions are:

• l1: l.d f4, 0(r1)
• l2: l.d f6, 0(r2)
• m1: mul.d f4,f4,f0
• m2: mul.d f6,f6,f2
• a1: add.d f4,f4,f6
• s1: s.d f4, 0(r1)

Constructing this graph involves identifying data dependencies among these instructions. The key dependencies involve the flow of data: the load instructions provide data for subsequent multiply and add instructions, which in turn provide data for the store instruction.

In the graph, nodes represent instructions, and directed edges indicate dependence. The gaps on edges denote the number of instructions or cycles between the producer and consumer, illustrating the potential for stalls and hazards.

Specifically, for the three flow-dependence types:

• FP arithmetic to FP arithmetic: dependencies from load to multiply and from multiply to add.
• FP arithmetic to FP store: dependency from add to store.
• FP load to FP arithmetic: dependencies from load instructions to subsequent arithmetic instructions.

The number of m-boxes in memory references is 1, and x-boxes in FP arithmetic are 4, affecting the dependence gaps.

b) Dependence-Induced Stalls

For each dependence type, the number of stalls between producer and consumer instructions as functions of '#m' and '#x' are:

• FP arith to FP arith: stalls depend on the latency of floating-point multiplications/additions, generally influenced by the number of x-boxes (e.g., 4 in this case).
• FP arith to FP store: depends on how quickly the result from the arithmetic can be stored, potentially limited by memory reference delays.
• FP load to FP arith: stalls are influenced by data load latency, directly related to the number of m-boxes, which is 1 in this scenario.

c) Stall Calculation for Specific Values

Given #m=1 and #x=4, and assuming known latencies (e.g., load latency of 1 cycle, FP operation latency of 4 cycles), calculating stalls involves summing the delays and pipeline hazards. The total stalls per iteration can be determined by analyzing the dependencies and their latencies through the method outlined in Chapter 3.

d) Loop Unrolling with Scheduling

Unrolling the loop twice effectively doubles the instructions, offering more opportunities for scheduling and reducing stalls. Optimal rescheduling places independent instructions together, minimizing hazards. Keeping the branch at the end, the restructured code reduces stalls to a minimum, with only unavoidable hazards remaining from the dependence gaps.

e) Increased 'mul-add' Dependence Gap

Increasing the dependence gap to 5 cycles and unrolling three times intensifies the challenge in scheduling. Optimally rescheduled, the loop can still minimize stalls but cannot eliminate them entirely. The number of stalls left depends on how well the instructions are scheduled relative to the increased latency, with the most complex cases leaving approximately 2 stalls, as illustrated.

Dynamic Instruction Scheduling I

a) Reservation Stations Content (Before Loads Complete)

Reservation stations track operand validity and hold instructions until operands are ready. For instructions l1 to s1, the stations initially contain the following:

• rs1(l1): empty or pending load result with no operands yet
• rs2(l2): similarly, pending or ready depending on load completion
• rs3(m1): waiting for f4, possibly pending load completion
• rs4(m2): waiting for f6
• rs5(a1): waiting for both f4 and f6, depending on their readiness
• rs6(s1): waiting for f4 to store, with load completed or pending

Initially, all loads are unresolved, so their operands are marked 'blank' in their stations, and dependencies are unresolved.

b) Reservation Stations After Loads Complete

Once load instructions l1 and l2 complete, their data are available. Reservation stations update to reflect this, with the load results now available, and dependent instructions' operands marked as valid. The stations now contain:

• rs1(l1): result available, instruction complete
• rs2(l2): result available, instruction complete
• rs3(m1): waiting for f4 (now available)
• rs4(m2): waiting for f6 (now available)
• rs5(a1): with f4 and f6 ready, can proceed
• rs6(s1): waiting for f4 to perform store

Remaining stations with instructions pending execution are marked accordingly, and the ones with data are marked 'free' or 'ready'.

c) Reservation Stations After Dispatching Next Iteration

Dispatching instructions l3 and l4 for the next iteration involves inserting them into rs1 and rs2. The first load has completed, so these new loads are pending, with their operands marked as pending until memory loads complete. The station contents update to:

• rs1(l3): new load pending
• rs2(l4): next load pending
• rs3(m1): completed from previous iteration
• others as per the new instructions

Dynamic Instruction Scheduling II

a) Flow Dependence Analysis

In the original code, a flow dependence exists from the add instruction (a1) to the store instruction (s1). This dependence is safe as it enforces correct write order and does not harm execution, since the store depends on the completion of the addition operation.

b) Antidependence Analysis

Antidependences, such as from s1 (store) to a subsequent instruction that overwrites the register, are not harmful here if correctly scheduled, because the store does not overwrite a register but writes to memory after the data is ready, thus preserving program correctness.

c) Output Dependence Analysis

The output dependence between instructions that write to the same register can be safely ignored here if the instructions are ordered correctly, especially as the store affects memory, not registers directly, and the code sequence respects proper data flow.

Load and Store Buffer Operations

a) Uniform Issue Delay in Code Sequences

Ignoring register dependence but respecting memory dependence ensures correctness because the load-buffer and store-buffer manage timing such that a store to memory completes before a dependent load issues. Both code sequences maintain correctness since load instructions look for the completion of prior stores, avoiding hazards.

b) Delay in Issue Due to Memory Dependence

Operationally, delaying the load until the store completes means that the load does not issue until the store writes the data to memory. 'Completion' involves the store buffer confirming data has been written back and made visible to subsequent loads, ensuring no stale or incorrect data is fetched.

c) Difference Between Speculated Load and Store

A speculated load can advance further through pipeline stages because it reads data independently, assuming no pending store conflicts. In contrast, a speculated store must wait until its data has been written to memory safely, since stores affect memory state directly. This difference enhances instruction-level parallelism while maintaining correctness, especially in out-of-order execution contexts.

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