EECE 343 Lab 2 Fall 2016: Value Display In Hex And Dec

EECE 343 Lab 2 Fall 2016 Lab 2: Value Display in Hex and Decimal

Implement a hierarchical design using Verilog submodules that extends the adder from Lab 1 to display the operands and sum on the DE2 board's 7-segment displays. The design should be combinational, updating displays in real-time as inputs from switches change. You will develop a testbench for a submodule, specifically a BCD converter, and implement the design according to specified display formats.

The input operands are 8-bit values received from specific switches on the DE2. SW[16:9] provides the first operand, and SW[7:0] provides the second operand. SW[8] and SW[17] are unused. The operands are displayed in hexadecimal on HEX7 through HEX4, with HEX7 displaying the more significant digit of the first operand, and HEX6 the less significant; similarly, HEX5 and HEX4 display the second operand.

The sum of the operands, which can be up to 9 bits, is displayed in decimal on HEX3 through HEX0. A provided BCD converter module is used to convert the binary sum into BCD format for display. The result's most significant digit appears on HEX3, and the least on HEX0.

The project includes a testbench for the BCD converter, which should exhaustively test all possible input values and display verification messages. Other module testbenches are encouraged but not mandatory. The design will be evaluated based on the correctness of operand and result displays and the thoroughness of the BCD converter testing.

Ensure your design is implemented as specified, correctly displays data as per formatting rules, and contains a comprehensive testbench for the BCD converter. Submit your project as an archive file, verifying correctness by restoring and testing the archive before submission.

Paper For Above instruction

The goal of this lab is to develop a hierarchical digital system utilizing Verilog hardware description language, specifically focusing on displaying addition results in both hexadecimal and decimal formats on a DE2 FPGA board. Core to the project are the principles of modular design, combinational logic, and verification through simulation. This comprehensive task enables students to reinforce their understanding of digital design, FPGA implementation, and testing methodologies.

Firstly, the lab task involves creating a combinational circuit that takes two 8-bit operands from switches SW[16:9] and SW[7:0], displays these operands in hexadecimal format on a set of four 7-segment displays, and computes their sum. The sum, which can be up to 9 bits, must then be converted to BCD for decimal display on four additional 7-segment displays.

A key challenge is translating binary sums into human-readable decimal format, which necessitates implementing or utilizing an existing BCD converter module. This module takes the 9-bit sum input and outputs the appropriate BCD digits. The project’s design must be hierarchical, meaning various submodules—such as the adder and BCD converter—are instantiated within a top-level module, allowing for better organization and reusability.

The display format specifications specify that the first and second operands are shown in hexadecimal with the most significant digit on HEX7 and HEX6 for the first operand, and HEX5 and HEX4 for the second operand. The final sum is displayed in decimal with the most significant digit on HEX3, progressing to the least significant digit on HEX0.

To verify the correctness of the BCD converter, students are required to develop a testbench that exhaustively tests all possible 9-bit inputs, ensuring the BCD output correctly represents the decimal equivalent. This involves generating all possible binary sums, converting them, and checking correctness via simulation. Including informative debugging messages enhances validation.

Implementation involves several critical steps:

1. Developing or reusing an adder module for adding the two operands, ensuring it's combinational for instant updates on input changes.
2. Designing a BCD converter module to handle binary-to-BCD conversion, suitable for 9-bit inputs, possibly involving division and modulus operations.
3. Creating a top-level module to instantiate and connect the adder and BCD converter modules, handle switch inputs, and manage 7-segment display outputs.
4. Ensuring correct display logic so each 4-bit BCD digit maps to the corresponding 7-segment encoding, with the display formats matching specifications.
5. Developing a comprehensive testbench for the BCD converter that tests all input possibilities and reports validation results.

In addition to the core functional requirements, students must program the FPGA with correct pin constraints as per the DE2 user manual, ensuring accurate physical implementation. Proper simulation and debugging are crucial steps before hardware programming, validating that the displays show correct and timely data in response to switches.

Overall, this assignment emphasizes practical skills in digital design, hierarchical modules, simulation-based verification, and hardware implementation. Mastery of these concepts is essential for students pursuing careers in digital systems design, embedded systems, and FPGA-based development.

References

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