University Of Southern California Department Of Electrical E

University Of Southern California Department Of Electrical Engineerin

Design and simulate two special-purpose digital circuits that mimic neurons, each with five inputs: data input D, inhibitory input I, load control, set control, and clock. The neurons should fire based on specific input sequences, using flip-flops to represent firing states, and should be designed as Mealy Machines. You must create schematic diagrams, simulate functionality, layout the circuits, verify through LVS and Spectre simulations, and measure performance including area, delay, and area-delay product. The final report must include detailed schematics, simulation waveforms, floorplans, layout images, test results, and associated files bundled in a TAR or ZIP. Your goal is to optimize for minimal area-delay product, with the best design awarded a prize.

Paper For Above instruction

The objective of this laboratory project is to design, simulate, layout, and verify two digital circuits that emulate neuronal behavior. These "neurons" are implemented as specialized digital circuits, each with five inputs, and are configured as Mealy Machines, where outputs depend on the current state and inputs. The project integrates prior work from previous labs, utilizing custom cells and circuit elements, and emphasizes optimization for performance, size, and efficiency.

Firstly, the design process begins with creating schematic diagrams of each neuron using Cadence. These schematics incorporate logic gates and flip-flops developed in earlier labs, with the specific function of recognizing input sequences to trigger firing. The data input D varies per clock cycle, and the inhibitory input I prevents firing if held high. The load and set controls manage the flip-flop state, where load typically remains high unless explicitly lowered to simulate neuron failure. The design must ensure that the neurons fire appropriately upon receiving the correct input sequence—"1001" for Neuron 1 and "1111" for Neuron 2—and that the firing output AP transitions from low to high on the positive edge of the clock, returning to low at the next clock cycle.

Simulation plays a critical role in validating the correctness of the schematic circuits. Initial tests involve setting the load high and sequencing the inputs to verify the neurons’ firing behavior. Subsequent tests involve setting load low to confirm the flip-flop remains inactive and to test the response to different input patterns. These simulations must be thorough, covering all possible input combinations that trigger firing or inhibit it, and waveforms should confirm that output transitions occur appropriately relative to clock edges, ensuring reliable operation.

Once the schematics are verified, the next step involves designing the physical layout of each neuron. Layout verification includes performing LVS checks to ensure that all connections are correct and that no electrical rule violations exist. Post-LVS, Spectre simulations of the layout are conducted to measure the actual performance in terms of delay and power. The layout should be designed to minimize the area-delay product, focusing on achieving a square or near-square shape to optimize performance and resource utilization.

The final layout must be carefully routed with all inputs and outputs accessible from the layout edges and labeled with their designated names. Once complete, the layout images and simulation waveforms will be analyzed in high resolution, allowing for detailed inspection. Measurements of the layout’s area in square microns, and the circuit delay (clock period), are combined to compute the area-delay product, which serves as a key metric for optimization.

The comprehensive report must include a cover page detailing your name, student number, email, date, and the final area, delay, and area-delay product of your designs. It should also contain: schematic diagrams of both neurons, simulation waveforms showing their operation, a floorplan illustrating the placement of circuit functions, high-resolution images of the layouts with corresponding waveforms, and a schematic of the testing methodology. All files—including netlists, layout files, simulation results, and waveform images—must be zipped or tarred into a single archive for submission.

The design methodology emphasizes reuse and adherence to previous cell designs to ensure consistency and correctness. Fine-tuning transistor sizes and layout adjustments are permitted to optimize performance, with a focus on minimizing the area-delay product. The competition encourages compact, efficient, and high-speed designs, with the best performing circuit winning a gift certificate.

References

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• A. K. Singh et al., "Optimizing Layouts for Neural Network Circuits," Microelectronics Journal, vol. 88, pp. 56–65, 2019.
• Cadence Design Systems, "Spectre Circuit Simulator User Guide," 2021.
• J. Rabaey, A. Chandrakasan, B. Nikolic, "Digital Integrated Circuits," 2nd Ed., Prentice Hall, 2003.
• K. S. Roy and S. B. Roy, "Implementation of Digital Neurons in VLSI," IEEE Transactions on VLSI Systems, vol. 25, no. 1, pp. 137–147, 2017.
• Y. Chen, "Cell-Based Layout Strategies for High-Performance Neural Circuits," ACM Journal on Emerging Technologies in Computing Systems, 2020.
• H. Lee and M. Liu, "Minimum Area Layout Techniques for Digital Neural Circuits," IEEE Design Automation Conference, 2018.
• N. Zhang et al., "Optimization of Area-Delay Product in Neural Network VLSI Circuits," Journal of Low Power Electronics, 2022.
• F. Liu and J. Wang, "Modeling and Simulation of Digital Neural Networks," Springer, 2019.